Building a Risc-V cpu Core Training Logo

Building a Risc-V cpu Core Training

Live Online & Classroom Enterprise Training

This Course is about Creating a RISC-V CPU with modern open-source circuit design tools, methodologies, and microarchitecture, all from your browser.

Looking for a private batch ?

REQUEST A CALLBACK

Need help finding the right training?

Your Message

  • Enterprise Reporting

  • Lifetime Access

  • CloudLabs

  • 24x7 Support

  • Real-time code analysis and feedback

What is Building a Risc-V cpu Core Training about?

This course will guide developers to understanding the ‘rules of the road’ of creating open-source software, either as a newbie or as someone with experience primarily in creating and working with proprietary code.

What are the objectives of Building a Risc-V cpu Core Training ?

Explain Digital logic design (combinational and sequential logic)

Discuss RISC-V (RV32I) instruction set architecture

Discuss Basic CPU microarchitecture

Understand Transaction-Level Verilog basics

Discuss Maker chip online IDE

Who is Building a Risc-V cpu Core Training for?

Building a RISC-V CPU Core is designed for anyone with a technical inclination who is interested in learning more about hardware.

What are the prerequisites for Building a Risc-V cpu Core Training?

None

Available Training Modes

Live Online Training

14 Hours

Self-Paced Training

7 Hours

Course Outline Expand All

Expand All

  • • Overview
  • • Maker chip IDE and Resources
  • • Overview
  • • Combinational Logic
  • • Arithmetic Logic
  • • Multiplexers
  • • Literals and Concatenation
  • • Visual Debug
  • • File Structure and Tool Flow
  • • Sequential Logic
  • • Overview
  • • Software, Compilers & CPUs
  • • RISC-V
  • • Overview
  • • CPU Labs Setup
  • • CPU Microarchitecture & Implementation Plan
  • • PC Logic
  • • Instruction Memory
  • • Decode Logic
  • • Register File Read
  • • Arithmetic Logic Unit
  • • Register File Write
  • • Branch Logic
  • • Overview
  • • Test Program
  • • Decode Logic
  • • Arithmetic Logic Unit
  • • Jump Logic
  • • Load, Store, and Data Memory
  • • What's Next?

Who is the instructor for this training?

The trainer for this Building a Risc-V cpu Core Training has extensive experience in this domain, including years of experience training & mentoring professionals.

Reviews