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SOC Design Training

Live Online & Classroom Enterprise Training

Covers the architecture and operation of a Security Operations Center. Includes incident response design, alert management, and threat monitoring.

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What is SOC Design Training about?

The SOC Design course provides comprehensive knowledge of planning, building, and optimizing a Security Operations Center (SOC). Participants will understand the essential components of SOC architecture, technology stack, processes, and team structure. The training covers use case design, threat detection strategy, log management, automation, and metrics to ensure an efficient and scalable SOC. By the end of this course, learners will be able to align SOC design with business objectives and compliance requirements while enhancing an organization’s cybersecurity resilience.

What are the objectives of SOC Design Training ?

  • Understand SOC architecture, design principles, and operational models. 
  • Plan and build SOC infrastructure with the right tools and technologies. 
  • Develop threat detection, incident response, and escalation workflows. 
  • Implement SIEM, SOAR, and log management best practices. 
  • Align SOC operations with compliance and business objectives. 

Who is SOC Design Training for?

  • Cybersecurity Architects and Engineers. 
  • SOC Managers and Analysts. 
  • IT Security Consultants and System Integrators. 
  • Network Security Professionals. 
  • Professionals involved in building or enhancing SOC capabilities.

What are the prerequisites for SOC Design Training?

Prerequisites:  

  • Basic understanding of cybersecurity concepts and frameworks. 
  • Familiarity with SIEM tools (e.g., Splunk, QRadar, Azure Sentinel). 
  • Knowledge of network and endpoint security fundamentals. 
  • Experience in incident detection or security monitoring (recommended). 
  • Awareness of compliance standards like ISO 27001, NIST, or MITRE ATT&CK. 

Learning Path: 

  • Introduction to SOC Fundamentals and Objectives 
  • SOC Architecture and Design Framework 
  • Technology Stack – SIEM, SOAR, Threat Intelligence, and Analytics 
  • Process Design – Use Cases, Workflows, and Playbooks 
  • SOC Optimization – KPIs, Automation, and Continuous Improvement 

Related Courses: 

  • SOC Operations and Management 
  • SIEM Implementation and Administration 
  • Threat Hunting and Incident Response 
  • Cyber Threat Intelligence Fundamentals

Available Training Modes

Live Online Training

4 Days

Course Outline Expand All

Expand All

  • SOC design & verification flow overview
  • SOC Design concepts
  • Processor boot concepts
  • SOC Verification: Important aspects
  • Testbench
  • Setting up SOC TB environment
  • SOC Subsystem overview (Processor, High speed, Low speed, Modem, Multimedia subsystem)
  • Testplan
  • Testcase Flow
  • Testcase Coding (C & SV)
  • Running testcases & regression
  • SOC Test debug
  • Typical testcase issues
  • Verification closure
  • Performance requirements
  • Gate level simulations
  • Power Aware Simulations
  • PAGLS
  • EVCD generation
  • Vector runs on VT setup
  • Generating binaries for running on tester
  • ECO
  • RMA
  • UVC in Testbench setup & sequence usage in SV testcase
  • SoC Architecture
  • Design Integration
  • Spyglass
  • Functional Verification
  • Formal Verification (Connectivity Checks)
  • PA RTL simulations
  • GLS
  • PA GLS simulations (UPF)
  • Vector EVCD generation
  • VT simulations on testers
  • Post silicon validation (VI)
  • SoC Architecture
  • SoC Interconnects & NOCs
  • NoC Overview – Types of NOCs, purpose and diagram
  • SoC Digital & Analog Components
  • SoC Address Mapping
  • SoC Interrupt Mapping
  • SoC Frequency Plan
  • SoC Performance requirements
  • Features
  • DPLL
  • SoC Memories: Msg ram, Iram, DDR, Flash
  • SoC Subsystems
  • Low Power Verification
  • UPF
  • SoC Architecture, understanding transaction matrix
  • Processor boot, SCF file
  • Interconnects
  • Memory preloading
  • DDR initialization
  • PLL locking (LMN values)
  • TIC interface
  • Clock domains
  • Different clock modes
  • XO mode, at-speed mode
  • Interrupt handler
  • Processor interfaces (instruction fetch, data code)
  • I/Os of SOC: Dedicated IOs, GPIOs
  • GPIO purpose: Pad muxing
  • CDC
  • Cycle slips
  • MMU, Physical address, Virtual address
  • ARM instruction set basics
  • Types of verification and their differences
  • Processor architectures: ARM, ARC, DSP
  • Cortex A series, M series
  • Impact on design architecture
  • Basics of ARM processors
  • Types of processors – Cortex-M series, A series
  • ARM C, ASM compiler, linker
  • Caches (L1 and L2)
  • Generic Interrupt Controller
  • Exceptions, Events – Types and handling
  • Debug system – Basics of ARM debug subsystem
  • Scatter files
  • Setting reset location to start booting
  • Loading C code into memories – Front door, back door
  • ARM Instruction example
  • SoC environment structure
  • SoC TB Architecture
  • Integrating UVC into SoC TB
  • SoC Processor-TB interaction
  • Register wr-rd, reset tests
  • Interrupt tests
  • Targeting different frequency plans
  • Feature (use-case) tests
  • Power aware tests
  • Fuse tests
  • End-to-end data transfer tests
  • Booting from different testcases
  • Address decoding access tests
  • Connectivity tests
  • TIC mode
  • Functional mode
  • Device Initialization
  • DDR initialization
  • Enabling DDR access to different processors
  • Processor boot sequence
  • Processor boot from different memories
  • C test main function
  • Power uncollapse
  • Functional test
  • Listing down test requirements, pass criteria
  • Power domains to be up
  • Clock domains to be up, required frequencies
  • Understanding required flow to implement testcase
  • Knowing library functions to implement above flow
  • Understanding handshake between Native & SV code
  • Design baseline
  • All design sub-component latest baselines
  • Verif baseline
  • All verif sub-component latest baselines
  • Updating environment for custom baseline
  • Command line
  • sim\_gui mode
  • Command line options
  • Using force files, timing corners, frequency plans
  • Tarmac log
  • List file
  • MPF file
  • Log
  • Wave dump debug
  • Message-based debug
  • Warnings, errors
  • Performance Management Approach
  • Tools and Resources
  • Capacity Planning and SizingProcessor not booting
  • Register looping
  • Not working at current frequency plan
  • PLL not locked
  • Memory not preloaded
  • Clocks not running
  • Access not enabled to register or memory space
  • Simulation not proceeding in time
  • Simulation proceeding but not completing (looping)
  • Interrupt not serviced
  • Interrupt not generated
  • Signal not sampled
  • Sub-module functional issues
  • Denali errors
  • Memory loading ‘x’ debug
  • Tied signals, unconnected ports
  • RTL code freeze
  • Base tapeout
  • Metal tapeout
  • ECO update
  • CS (customer shipment)
  • RMA
  • Regression 100% pass
  • 100% toggle coverage
  • High level & low-level reviews
  • Performance requirements
  • Power requirements met
  • Significance
  • Choosing tests for GLS
  • Format
  • Purpose
  • Choosing tests for GLS
  • Production vectors
  • Characterization vectors
  • Vector debug
  • When ECO is issued
  • Significance
  • SoC Interconnects
  • SoC Digital & Analog Components
  • SoC Address Mapping
  • SoC Interrupt Mapping
  • SoC Frequency Plan
  • SoC Performance requirements
  • Features
  • PLL
  • SoC Memories: Msg ram, Iram, DDR, Flash
  • Processor booting from different memories
  • UVC in Testbench setup & sequence usage in SV testcase

Who is the instructor for this training?

The trainer for this SOC Design Training has extensive experience in this domain, including years of experience training & mentoring professionals.

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